DATE 2001 Author Index

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

A

Abadir, M.
Full Chip False Timing Path Identification: Applications to the PowerPCTM Microprocessors [p. 514]
Aboulhamid, E.
A Methodology for Interfacing Open Source SystemC with a Third Party Software [p. 16]
Abraham, J.
Full Chip False Timing Path Identification: Applications to the PowerPCTM Microprocessors [p. 514]
Acosta, A.
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation Delay Model [p. 467]
Acosta, A.
Analog/Mixed-Signal IP Modeling for Design Reuse [p. 766]
Acquaviva, A.
An Adaptive Algorithm for Low-Power Streaming Multimedia Processing [p. 273]
Adler, T.
AnalogRouter: A New Approach of Current-Driven Routing for Analog Circuits [p. 819]
Agrawal, V.
Efficient Spectral Techniques for Sequential ATPG [p. 204]
Al-Ars, Z.
Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs [p. 496]
Alba Pinto, C.
Constraint Satisfaction for Storage Files with Fifos or Stacks during Scheduling [p. 824]
Al-Hashimi, B.
Dual Transitions Petri Net Based Modelling Technique for Embedded Systems Specification [p. 566]
Al-Hashimi, B.
Testability Trade-Offs for BIST RTL Data Paths: The Case for Three Dimensional Design Space [p. 802]
Ambler, T.
From DFT to Systems Test -- A Model Based Cost Optimization Tool [p. 302]
Ammer, M.
Design Methodology for PicoRadio Networks [p. 314]
Andrews, A.
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
Ashar, P.
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
Axelsson, Jakob
Methods and Tools for Systems Engineering of Automotive Electronic Architectures
Azaïs, F.
Implementation of a Linear Histogram BIST for ADCs [p. 590]
Azuma, M.
Clustering Based Fast Clock Scheduling for Light Clock-Tree [p. 240]

B

Badaroglu, M.
High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies [p. 326]
Badia, R.
A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures [p. 729]
Baghdadi, A.
An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC [p. 55]
Banerjee, P.
Precision and Error Analysis of MATLAB Applications during Automated Hardware Synthesis for FPGAs [p. 722]
Barke, E.
Architecture Driven Partitioning [p. 479]
Barke, E.
An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated Circuits [p. 807]
Bayraktaroglu, I.
Diagnosis for Scan-Based BIST: Reaching Deep into the Signatures [p. 102]
Bazargan-Sabet, P.
Modeling Crosstalk Noise for Deep Submicron Verification Tools [p. 530]
Beattie, M.
Efficient Inductance Extraction via Windowing [p. 430]
Behling, A.
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in Embedded Processors [p. 811]
Bekooij, M.
Power-Efficient Layered Turbo Decoder Processor [p. 246]
Bekooij, M.
Functional Units with Conditional Input/Output Behavior in VLIW Processors [p. 822]
Bellido, M.
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation Delay Model [p. 467]
Benabdenbi, M.
Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism [p. 150]
Benini, L.
Component Selection and Matching for IP-Based Design [p. 40]
Benini, L.
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
Benini, L.
An Adaptive Algorithm for Low-Power Streaming Multimedia Processing [p. 273]
Benini, L.
On-The-Fly Layout Generation for PTL Macrocells [p. 546]
Benso, A.
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection Environment [p. 219]
Bernard, S.
Implementation of a Linear Histogram BIST for ADCs [p. 590]
Bertoni, G.
Efficient Finite Field Digit-Serial Multiplier Architecture for Cryptography Applications [p. 812]
Bertrand, Y.
Implementation of a Linear Histogram BIST for ADCs [p. 590]
Bhadra, J.
Full Chip False Timing Path Identification: Applications to the PowerPCTM Microprocessors [p. 514]
Bjorkman, M.
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
Bois, G.
A Methodology for Interfacing Open Source SystemC with a Third Party Software [p. 16]
Bolsens, I.
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
Bolsens, I.
High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies [p. 326]
Braun, G.
Generating Production Quality Software Development Tools Using a Machine Description Language [p. 674]
Brayton, R.
Using SAT for Combinational Equivalence Checking [p. 114]
Breveglieri, L.
Efficient Finite Field Digit-Serial Multiplier Architecture for Cryptography Applications [p. 812]
Bromley, P.
Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools [p. 420]
Bunnbauer, W.
Annotated Data Types for Addressed Token Passing Networks [p. 801]
Burdiek, B.
Generation of Optimum Test Stimuli for Nonlinear Analog Circuits Using Nonlinear Programming and Time -Domain Sensitivities [p. 603]
Busá, N.
Functional Units with Conditional Input/Output Behavior in VLIW Processors [p. 822]

C

Cabodi, G.
Biasing Symbolic Search by Means of Dynamic Activity Profiles [p. 9]
Camurati, P.
Biasing Symbolic Search by Means of Dynamic Activity Profiles [p. 9]
Cappuccino, G.
CMOS Sizing Rule for High Performance Long Interconnects [p. 817]
Casavant, A.
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
Castelli, G.
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
Castro-López, R.
Retargeting of Mixed-Signal Blocks for SoCs [p. 772]
Catthoor, F.
Cache Conscious Data Layout Organization for Embedded Multimedia Applications [p. 686]
Catthoor, F.
Task Concurrency Management Methodology Summary [p. 813]
Chakrabarti, P.
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component Descriptions [p. 4]
Chakrabarty, K.
Efficient Test Data Compression and Decompression for System-on-a-Chip Using Internal Scan Chains and Golomb Coding [p. 145]
Chakrabarti, A.
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component Descriptions [p. 4]
Chandra, A.
Efficient Test Data Compression and Decompression for System-on-a-Chip Using Internal Scan Chains and Golomb Coding [p. 145]
Chang, C.
In-Place Delay Constrained Power Optmization Using Functional Symmetries [p. 377]
Chang, N.
An Operation Rearrangement Technique for Power Optimization in VLIW Instruction Fetch [p. 809]
Charest, L.
A Methodology for Interfacing Open Source SystemC with a Third Party Software [p. 16]
Chatterjee, A.
Test Generation Based Diagnosis of Device Parameters for Analog Circuits [p. 596]
Chen, L.
Microprocessor Power Analysis by Labeled Simulation [p. 182]
Chen, T.
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
Chen, T.
On the Impact of On-Chip Inductance on Signal Nets under the Influence of Power Grid Noise [p. 451]
Cheng, D.
Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques [p. 233]
Cherubal, S.
Test Generation Based Diagnosis of Device Parameters for Analog Circuits [p. 596]
Cheung, C.
Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques [p. 233]
Cheung, P.
Heuristic Datapath Allocation for Multiple Wordlength Systems [p. 791]
Cheynet, P.
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
Chiusano, S.
On Applying the Set Covering Model to Reseeding [p. 156]
Choi, K.
Performance Improvement of Multi-Processor Systems Cosimulation Based on SW Analysis [p. 749]
Chojnacki, A.
High-Quality Sub-Function Construction in Functional Decomposition Based on Information Relationship Measures [p. 383]
Choudhary, A.
Precision and Error Analysis of MATLAB Applications during Automated Hardware Synthesis for FPGAs [p. 722]
Cichon, G.
Annotated Data Types for Addressed Token Passing Networks [p. 801]
Ciesielski, M.
LPSAT: A Unified Approach to RTL Satisfiability [p. 398]
Cocorullo, G.
CMOS Sizing Rule for High Performance Long Interconnects [p. 817]
Constantinides, G.
Heuristic Datapath Allocation for Multiple Wordlength Systems [p. 791]
Corno, F.
On the Test of Microprocessor IP Cores [p. 209]
Cossement, N.
Task Concurrency Management Methodology Summary [p. 813]
Couderc, Damien
AIL: description of a global electronic architecture at the vehicle scale

D

da Silva Jr., J.
Design Methodology for PicoRadio Networks [p. 314]
Damasevicius, R.
Two Approaches for Developing Generic Components in VHDL [p. 800]
Dasgupta, P.
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component Descriptions [p. 4]
de la Rosa, J.
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
De Man, H.
High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies [p. 326]
De Man, H.
Cache Conscious Data Layout Organization for Embedded Multimedia Applications [p. 686]
De Man, H.
Task Concurrency Management Methodology Summary [p. 813]
De Micheli, G.
Component Selection and Matching for IP-Based Design [p. 40]
del Río, R.
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
Delgado-Restituto, M.
Retargeting of Mixed-Signal Blocks for SoCs [p. 772]
Demir, A.
CAD for RF Circuits [p. 520]
Demmeler, T.
A Universal Communication Model for an Automotive System Integration Platform [p. 47]
Dessouky, M.
Analog Design for Reuse -- Case Study: Very Low-Voltage Sigma-Delta Modulator [p. 353]
Di Carlo, S.
On Applying the Set Covering Model to Reseeding [p. 156]
Di Carlo, S.
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection Environment [p. 219]
Di Natale, G.
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection Environment [p. 219]
Dielissen, J.
Power-Efficient Layered Turbo Decoder Processor [p. 246]
Doboli, A.
Integrated Hardware-Software Co-Synthesis and High-Level Synthesis for Design i of Embedded Systems under Power and Latency Constraints [p. 612]
Doboli, A.
A Regularity-Based Hierarchical Symbolic Analysis Method for Large-Scale Analog Networks [p. 806]
Donnay, S.
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
Donnay, S.
High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies [p. 326]
Dorsch, R.
Using Mission Logic for Embedded Testing [p. 805]
Drechsler, R.
Spectral Decision Diagrams Using Graph Transformations [p. 713]
Drozd, A.
Efficient On-Line Testing Method for a Floating-Point Adder [p. 307]
Dutt, N.
Access Pattern Based Local Memory Customization for Low Power Embedded Systems [p. 778]

E

Eberle, W.
CAD for RF Circuits [p. 520]
Economakos, G.
Behavioral Synthesis with SystemC [p. 21]
Engels, L.
Functional Units with Conditional Input/Output Behavior in VLIW Processors [p. 822]
Engels, M.
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
Engels, M.
High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies [p. 326]
Entrena, L.
Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization [p. 391]
Espejo, J.
Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization [p. 391]

F

Favalli, M.
Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors [p. 290]
Fekete, S.
Optimal FPGA Module Placement with Temporal Precedence Constraints [p. 658]
Fernández, F.
Retargeting of Mixed-Signal Blocks for SoCs [p. 772]
Ferrandi, F.
Functional Test Generation for Behaviorally Sequential Models [p. 403]
Ferrara, G.
Functional Test Generation for Behaviorally Sequential Models [p. 403]
Fin, A.
Functional Test Generation for Behaviorally Sequential Models [p. 403]
Fiori, F.
Analysis of EME Produced by a Microcontroller Operation [p. 341]
Fiori, F.
Susceptibility of Analog Cells to Substrate Interference [p. 814]
Fragneto, P.
Efficient Finite Field Digit-Serial Multiplier Architecture for Cryptography Applications [p. 812]
Fummi, F.
Functional Test Generation for Behaviorally Sequential Models [p. 403]

G

Gangwal, O.
On Automatic Analysis of Geometrically Proximate Nets in VLSI Layout [p. 818]
Gao, Y.
A Graph Based Algorithm for Optimal Buffer Insertion under Accurate Delay Models [p. 535]
Garbe, H.
Modeling Electromagnetic Emission of Integrated Circuits for System Analysis [p. 336]
Garnica, O.
A Pseudo Delay-Insensitive Timing Model to Synthesizing Low-Power Asynchronous Circuits [p. 810]
Gauthier, L.
Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software [p. 679]
Gerfers, F.
A Design Strategy for Low-Voltage Low-Power Continuous-Time Sigma-Delta A/D Converters [p. 361]
Gerlach, J.
The Simulation Semantics of SystemC [p. 64]
Ghez, C.
Cache Conscious Data Layout Organization for Embedded Multimedia Applications [p. 686]
Giani, A.
Efficient Spectral Techniques for Sequential ATPG [p. 204]
Gielen, G.
Efficient Time -Domain Simulation of Telecom Frontends Using a Complex Damped Exponential Signal Model [p. 169]
Gielen, G.
High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies [p. 326]
Giusto, P.
A Universal Communication Model for an Automotive System Integration Platform [p. 47]
Giusto, P.
Reliable Estimation of Execution Time of Embedded Software [p. 580]
Gizopoulos, D.
Deterministic Software -Based Self-Testing of Embedded Processor Cores [p. 92]
Goldberg, E.
Using SAT for Combinational Equivalence Checking [p. 114]
Goldberg, E.
An Efficient Learning Procedure for Multiple Implication Checks [p. 127]
Göttsche, R.
Crosstalk Noise in Future Digital CMOS Circuits [p. 331]
Gravot, V.
High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies [p. 326]
Greiner, A.
Analog Design for Reuse -- Case Study: Very Low-Voltage Sigma-Delta Modulator [p. 353]
Grun, P.
Access Pattern Based Local Memory Customization for Low Power Embedded Systems [p. 778]
Guo, C.
Design Methodology for PicoRadio Networks [p. 314]
Gupta, A.
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
Gupta, S.
Exact Fault Simulation for Systems on Silicon that Protects Each Core's Intellectual Property (IP) [p. 804]

H

Hajjar, A.
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
Haldar, M.
Precision and Error Analysis of MATLAB Applications during Automated Hardware Synthesis for FPGAs [p. 722]
Harcourt, E.
Reliable Estimation of Execution Time of Embedded Software [p. 580]
Harmsze, F.
Power-Efficient Layered Turbo Decoder Processor [p. 246]
Hartenstein, R.
A Decade of Reconfigurable Computing: A Visionary Retrospective [p. 642]
Hashimoto, K.
CPU for PlayStation®2 [p. 696]
Hashizume, M.
CMOS Open Defect Detection by Supply Current Test [p. 509]
Hering, K.
dlbSIM -- A Parallel Functional Logic Simulator Allowing Dynamic Load Balancing [p. 472]
Hermes, B.
Towards a Better Understanding of Failure Modes and Test Requirements of ADCs [p. 803]
Hermida, R.
A Pseudo Delay-Insensitive Timing Model to Synthesizing Low-Power Asynchronous Circuits [p. 810]
Hettich, G.
Vehicle Electric/Electronic Architecture -- One of the Most Important Challenges for OEM's [p. 112]
Hoffmann, A.
Generating Production Quality Software Development Tools Using a Machine Description Language [p. 674]
Hoffmann, A.
A Framework for Fast Hardware-Software Co-Simulation [p. 760]
Hoffmann, D.
The Simulation Semantics of SystemC [p. 64]
Hoffmann, D.
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata [p. 742]
Horta, N.
A SkillTM-Based Library for Retargetable Embedded Analog Cores [p. 768]
Hsiao, M.
Efficient Spectral Techniques for Sequential ATPG [p. 204]
Hsieh, C.
Microprocessor Power Analysis by Labeled Simulation [p. 182]
Hu, B.
In-Place Delay Constrained Power Optmization Using Functional Symmetries [p. 377]
Huang, Z.
Managing Dynamic Reconfiguration Overhead in Systems -On-A-Chip Design Using Reconfigurable Datapaths and Optimized Interconnection Networks [p. 735]
Huisken, J.
Power-Efficient Layered Turbo Decoder Processor [p. 246]
Hwang, T.
Binary Decision Diagram with Minimum Expected Path Length [p. 708]

I

Ichimiya, M.
CMOS Open Defect Detection by Supply Current Test [p. 509]
Ikumi, N.
CPU for PlayStation®2 [p. 696]
Ilponse, F.
Modeling Crosstalk Noise for Deep Submicron Verification Tools [p. 530]
Irion, A.
Circuit Partitioning for Efficient Logic BIST Synthesis [p. 86]
Ishihara, S.
Streaming BDD Manipulation for Large-Scale Combinatorial Problems [p. 702]
Iyer, A.
Power Aware Microarchitecture Resource Scaling [p. 190]

J

Jacobs, E.
Minimizing Stand-By Leakage Power in Static CMOS Circuits [p. 370]
Janicot, V.
Simulation Method to Extract Characteristics for Digital Wireless Communication Systems [p. 176]
Jerke, G.
AnalogRouter: A New Approach of Current-Driven Routing for Analog Circuits [p. 819]
Jerraya, A.
An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC [p. 55]
Jerraya, A.
A Model for Describing Communication between Aggregate Objects in the Specification and Design of Embedded Systems [p. 77]
Jerraya, A.
Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software [p. 679]
Jerraya, A.
Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design [p. 754]
Jess, J.
Constraint Satisfaction for Storage Files with Fifos or Stacks during Scheduling [p. 824]
Jingnan, X.
A SkillTM-Based Library for Retargetable Embedded Analog Cores [p. 768]
Jochens, G.
Automatic Nonlinear Memory Power Modelling [p. 808]
John, W.
Modeling Electromagnetic Emission of Integrated Circuits for System Analysis [p. 336]
Józwiak, L.
High-Quality Sub-Function Construction in Functional Decomposition Based on Information Relationship Measures [p. 383]
Juan-Chico, J.
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation Delay Model [p. 467]
Jung, J.
Performance Improvement of Multi-Processor Systems Cosimulation Based on SW Analysis [p. 749]
Jutman, A.
Timing Simulation of Digital Circuits with Binary Decision Diagrams [p. 460]

K

Kaiser, A.
Analog Design for Reuse -- Case Study: Very Low-Voltage Sigma-Delta Modulator [p. 353]
Kalla, P.
LPSAT: A Unified Approach to RTL Satisfiability [p. 398]
Karim, F.
Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools [p. 420]
Kiefer, G.
Circuit Partitioning for Efficient Logic BIST Synthesis [p. 86]
Kim, J.
An Operation Rearrangement Technique for Power Optimization in VLIW Instruction Fetch [p. 809]
Kogel, T.
A Framework for Fast Hardware-Software Co-Simulation [p. 760]
Koh, C.
Repeater Block Planning under Simultaneous Delay and Transition Time Constraints [p. 540]
Köhler, E.
Optimal FPGA Module Placement with Temporal Precedence Constraints [p. 658]
Koranne, S.
On Automatic Analysis of Geometrically Proximate Nets in VLSI Layout [p. 818]
Kralicek, P.
Modeling Electromagnetic Emission of Integrated Circuits for System Analysis [p. 336]
Krampl, G.
Modelling SoC Devices for Virtual Test Using VHDL [p. 770]
Kranitis, N.
Deterministic Software -Based Self-Testing of Embedded Processor Cores [p. 92]
Krishna, S.
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component Descriptions [p. 4]
Kropf, T.
The Simulation Semantics of SystemC [p. 64]
Kropf, T.
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata [p. 742]
Kruse, L.
Automatic Nonlinear Memory Power Modelling [p. 808]
Kuh, E.
Explicit Formulas and Efficient Algorithm for Moment Computation of Coupled RC Trees with Lumped and Distributed Elements [p. 445]
Kulkarni, C.
Cache Conscious Data Layout Organization for Embedded Multimedia Applications [p. 686]
Küter, J.
Architecture Driven Partitioning [p. 479]

L

Lai, M.
Slicing Tree is a Complete Floorplan Representation [p. 228]
Lamm, H.
Design of Low-Power High-Speed Maximum a Priori Decoder Architectures [p. 258]
Lanchares, J.
A Pseudo Delay-Insensitive Timing Model to Synthesizing Low-Power Asynchronous Circuits [p. 810]
Larsson, E.
An Integrated System-On-Chip Test Framework [p. 138]
Lauwereins, R.
Task Concurrency Management Methodology Summary [p. 813]
Lavagno, L.
Generation of Minimal Size Code for Schedule Graphs [p. 668]
Lechner, A.
Towards a Better Understanding of Failure Modes and Test Requirements of ADCs [p. 803]
Li, J.
Memory Fault Diagnosis by Syndrome Compression [p. 97]
Li, S.
Design Methodology for PicoRadio Networks [p. 314]
Lienig, J.
AnalogRouter: A New Approach of Current-Driven Routing for Analog Circuits [p. 819]
Liu, C.
Binary Decision Diagram with Minimum Expected Path Length [p. 708]
Liu, S.
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
Liu, X.
A Static Power Estimation Methodology for IP-Based Design [p. 280]
Liu, Y.
Binary Decision Diagram with Minimum Expected Path Length [p. 708]
Lobachev, M.
Efficient On-Line Testing Method for a Floating-Point Adder [p. 307]
Long, D.
CAD for RF Circuits [p. 520]
López, J.
A Hardware-Software Operating System for Heterogeneous Designs [p. 820]
Löser, J.
dlbSIM -- A Parallel Functional Logic Simulator Allowing Dynamic Load Balancing [p. 472]
Louërat, M.
Analog Design for Reuse -- Case Study: Very Low-Voltage Sigma-Delta Modulator [p. 353]
Luk, W.
Heuristic Datapath Allocation for Multiple Wordlength Systems [p. 791]
Lyonnard, D.
An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC [p. 55]

M

Maaß, C.
From DFT to Systems Test -- A Model Based Cost Optimization Tool [p. 302]
Macchiarulo, L.
On-The-Fly Layout Generation for PTL Macrocells [p. 546]
Macii, A.
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
Macii, E.
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
Macii, E.
On-The-Fly Layout Generation for PTL Macrocells [p. 546]
Madrid, N.
Analog/Mixed-Signal IP Modeling for Design Reuse [p. 766]
Majauskas, G.
Two Approaches for Developing Generic Components in VHDL [p. 800]
Malik, S.
Managing Dynamic Reconfiguration Overhead in Systems -On-A-Chip Design Using Reconfigurable Datapaths and Optimized Interconnection Networks [p. 735]
Mandapati, A.
Implementation of the ATI Flipper Chip [p. 697]
Manoli, Y.
A Design Strategy for Low-Voltage Low-Power Continuous-Time Sigma-Delta A/D Converters [p. 361]
Marchal, P.
Task Concurrency Management Methodology Summary [p. 813]
Marculescu, D.
Power Aware Microarchitecture Resource Scaling [p. 190]
Marculescu, R.
Probabilistic Application Modeling for System-Level Performance Analysis [p. 572]
Marek-Sadowska, M.
In-Place Delay Constrained Power Optmization Using Functional Symmetries [p. 377]
Markwardt, J.
dlbSIM -- A Parallel Functional Logic Simulator Allowing Dynamic Load Balancing [p. 472]
Marichalar, Simon
AIL: description of a global electronic architecture at the vehicle scale
Maroufi, W.
Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism [p. 150]
Martin, G.
Reliable Estimation of Execution Time of Embedded Software [p. 580]
Marzouki, M.
Testing TAPed Cores and Wrapped Cores with the Same Test Access Mechanism [p. 150]
Mazumder, P.
Efficient and Passive Modeling of Transmission Lines by Using Differential Quadrature Method [p. 437]
Medeiro, F.
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
Mesman, B.
Constraint Satisfaction for Storage Files with Fifos or Stacks during Scheduling [p. 824]
Metra, C.
Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors [p. 290]
Meyr, H.
Generating Production Quality Software Development Tools Using a Machine Description Language [p. 674]
Meyr, H.
A Framework for Fast Hardware-Software Co-Simulation [p. 760]
Minato, S.
Streaming BDD Manipulation for Large-Scale Combinatorial Problems [p. 702]
Miranda, M.
Cache Conscious Data Layout Organization for Embedded Multimedia Applications [p. 686]
Mirkhani, S.
Adaptation of an Event-Driven Simulation Environment to Sequentially Propagated Concurrent Fault Simulation [p. 823]
Mohaupt, T.
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in Embedded Processors [p. 811]
Mooney III, V.
System-On-A-Chip Processor Synchronization Support in Hardware [p. 633]
Moya, F.
A Hardware-Software Operating System for Heterogeneous Designs [p. 820]
Moya, J.
A Hardware-Software Operating System for Heterogeneous Designs [p. 820]
Mueller, W.
The Simulation Semantics of SystemC [p. 64]
Muhammad, K.
Low Complexity FIR Filters Using Factorization of Perturbed Coefficients [p. 268]
Mukaiyama, A.
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
Müller, D.
SystemCSV -- An Extension of SystemC for Mixed Multi-Level Communication Modeling and Interface-Based System Design [p. 26]
Munn, I.
High Quality Behavioral Verification Using Statistical Stopping Criteria [p. 411]
Musolino, F.
Analysis of EME Produced by a Microcontroller Operation [p. 341]

N

Nagamatsu, M.
CPU for PlayStation®2 [p. 696]
Naidu, S.
Minimizing Stand-By Leakage Power in Static CMOS Circuits [p. 370]
Nam, G.
A Boolean Satisfiability-Based Incremental Rerouting Approach with Application to FPGAs [p. 560]
Nandi, A.
Abstraction of Word-Level Linear Arithmetic Functions from Bit-Level Component Descriptions [p. 4]
Nandi, A.
Probabilistic Application Modeling for System-Level Performance Analysis [p. 572]
Narita, S.
SH-4 RISC Microprocessor for Multimedia, Game Machine [p. 699]
Navabi, Z.
Adaptation of an Event-Driven Simulation Environment to Sequentially Propagated Concurrent Fault Simulation [p. 823]
Nayak, A.
Precision and Error Analysis of MATLAB Applications during Automated Hardware Synthesis for FPGAs [p. 722]
Neau, C.
Low Complexity FIR Filters Using Factorization of Perturbed Coefficients [p. 268]
Nebel, W.
Automatic Nonlinear Memory Power Modelling [p. 808]
Nguyen, L.
Simulation Method to Extract Characteristics for Digital Wireless Communication Systems [p. 176]
Nicolau, A.
Access Pattern Based Local Memory Customization for Low Power Embedded Systems [p. 778]
Nicolescu, B.
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
Nicolescu, G.
A Model for Describing Communication between Aggregate Objects in the Specification and Design of Embedded Systems [p. 77]
Nicolescu, G.
Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design [p. 754]
Nicolici, N.
Testability Trade-Offs for BIST RTL Data Paths: The Case for Three Dimensional Design Space [p. 802]
Nikolic, B.
Design Methodology for PicoRadio Networks [p. 314]
Noguera, J.
A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures [p. 729]
Nohl, A.
Generating Production Quality Software Development Tools Using a Machine Description Language [p. 674]
Novikov, Y.
An Efficient Learning Procedure for Multiple Implication Checks [p. 127]

O

Oikonomakos, P.
Behavioral Synthesis with SystemC [p. 21]
Olbrich, M.
An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated Circuits [p. 807]
Olías, E.
Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization [p. 391]
Omnès, T.
Low-Power Systems on Chips (SOCs) [p. 488]
Orailoglu, A.
Diagnosis for Scan-Based BIST: Reaching Deep into the Signatures [p. 102]
Ouaiss, I.
Hierarchical Memory Mapping during Synthesis in FPGA -Based Reconfigurable Computers [p. 650]

P

Panagopoulos, I.
Behavioral Synthesis with SystemC [p. 21]
Papaefthymiou, C.
A Static Power Estimation Methodology for IP-Based Design [p. 280]
Papakonstantinou, G.
Behavioral Synthesis with SystemC [p. 21]
Parameswaran, S.
Code Placement in Hardware Software Co -Synthesis to Improve Performance and Reduce Cost [p. 626]
Paschalis, A.
Deterministic Software -Based Self-Testing of Embedded Processor Cores [p. 92]
Passerone, C.
Generation of Minimal Size Code for Schedule Graphs [p. 668]
Paulin, P.
Network Processors: A Perspective on Market Requirements, Processor Architectures and Embedded S/W Tools [p. 420]
Pedram, M.
Microprocessor Power Analysis by Labeled Simulation [p. 182]
Pees, S.
Generating Production Quality Software Development Tools Using a Machine Description Language [p. 674]
Peng, Z.
An Integrated System-On-Chip Test Framework [p. 138]
Peng, Z.
Timing Simulation of Digital Circuits with Binary Decision Diagrams [p. 460]
Peralías, E.
Analog/Mixed-Signal IP Modeling for Design Reuse [p. 766]
Pérez-Verdú, B.
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
Pflanz, M.
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in Embedded Processors [p. 811]
Phillips, J.
CAD for RF Circuits [p. 520]
Piguet, C.
Low-Power Systems on Chips (SOCs) [p. 488]
Pileggi, L.
Efficient Inductance Extraction via Windowing [p. 430]
Pol, E.
PRMDL: A Machine Description Language for Clustered VLIW Architectures [p. 821]
Pomeranz, I.
Sequence Reordering to Improve the Levels of Compaction Achievable by Static Compaction Procedures [p. 214]
Pomeranz, I.
Definitions of the Numbers of Detections of Target Faults and their Effectiveness in Guiding Test Generation for High Defect Coverage [p. 504]
Poncino, M.
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
Poulakis, I.
Behavioral Synthesis with SystemC [p. 21]
Prasad, M.
Using SAT for Combinational Equivalence Checking [p. 114]
Prayati, A.
Task Concurrency Management Methodology Summary [p. 813]
Prinetto, P.
On Applying the Set Covering Model to Reseeding [p. 156]
Prinetto, P.
SEU Effect Analysis in an Open-Source Router via a Distributed Fault Injection Environment [p. 219]
Psarakis, M.
Deterministic Software -Based Self-Testing of Embedded Processor Cores [p. 92]

Q

Quasem, M.
Exact Fault Simulation for Systems on Silicon that Protects Each Core's Intellectual Property (IP) [p. 804]
Quer, S.
Biasing Symbolic Search by Means of Dynamic Activity Profiles [p. 9]

R

Rabaey, J.
Design Methodology for PicoRadio Networks [p. 314]
Radhakrishnan, R.
On the Verification of Synthesized Designs Using Automatically Generated Transformational Witnesses [p. 798]
Rahman, M.
From DFT to Systems Test -- A Model Based Cost Optimization Tool [p. 302]
Ramacher, U.
Crosstalk Noise in Future Digital CMOS Circuits [p. 331]
Rebaudengo, M.
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
Reda, S.
Combinational Equivalence Checking Using Boolean Satisfiability and Binary Decision Diagrams [p. 122]
Reddy, S.
Sequence Reordering to Improve the Levels of Compaction Achievable by Static Compaction Procedures [p. 214]
Reddy, S.
Definitions of the Numbers of Detections of Target Faults and their Effectiveness in Guiding Test Generation for High Defect Coverage [p. 504]
Reid, M.
A Methodology for Interfacing Open Source SystemC with a Third Party Software [p. 16]
Rein, A.
An Improved Hierarchical Classification Algorithm for Structural Analysis of Integrated Circuits [p. 807]
Renaudin, M.
Low-Power Systems on Chips (SOCs) [p. 488]
Renovell, M.
Implementation of a Linear Histogram BIST for ADCs [p. 590]
Riccó, B.
An Adaptive Algorithm for Low-Power Streaming Multimedia Processing [p. 273]
Richardson, A.
Towards a Better Understanding of Failure Modes and Test Requirements of ADCs [p. 803]
Rodríguez-Vázquez, A.
Top-Down Design of a xDSL 14-bit 4MS/s Sigma-Delta Modulator in Digital CMOS Technology [p. 348]
Rodríguez-Vázquez, A.
Retargeting of Mixed-Signal Blocks for SoCs [p. 772]
Rolain, Y.
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
Rona, M.
Modelling SoC Devices for Virtual Test Using VHDL [p. 770]
Rosenstiehl, W.
The Simulation Semantics of SystemC [p. 64]
Rosenstiel, W.
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata [p. 742]
Rousselle, C.
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in Embedded Processors [p. 811]
Roy, K.
Low Complexity FIR Filters Using Factorization of Perturbed Coefficients [p. 268]
Roychowdhury, J.
CAD for RF Circuits [p. 520]
Rueda, A.
Analog/Mixed-Signal IP Modeling for Design Reuse [p. 766]
Ruf, J.
The Simulation Semantics of SystemC [p. 64]
Ruf, J.
Simulation-Guided Property Checking Based on a Multi-Valued AR-Automata [p. 742]
Rutenbar, R.
A Boolean Satisfiability-Based Incremental Rerouting Approach with Application to FPGAs [p. 560]

S

Saglam, B.
System-On-A-Chip Processor Synchronization Support in Hardware [p. 633]
Saitoh, M.
Clustering Based Fast Clock Scheduling for Light Clock-Tree [p. 240]
Sakallah, K.
A Boolean Satisfiability-Based Incremental Rerouting Approach with Application to FPGAs [p. 560]
Salem, A.
Combinational Equivalence Checking Using Boolean Satisfiability and Binary Decision Diagrams [p. 122]
Sami, M.
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors [p. 252]
San Millán, E.
Generalized Reasoning Scheme for Redundancy Addition and Removal Logic Optimization [p. 391]
Sangiovanni-Vincentelli, A.
Design Methodology for PicoRadio Networks [p. 314]
Sansen, W.
Efficient Time -Domain Simulation of Telecom Frontends Using a Complex Damped Exponential Signal Model [p. 169]
Sarkar, P.
Repeater Block Planning under Simultaneous Delay and Transition Time Constraints [p. 540]
Sawitzki, S.
Power-Efficient Layered Turbo Decoder Processor [p. 246]
Scarsi, R.
Extending Lifetime of Portable Systems by Battery Scheduling [p. 197]
Schmidt, E.
Automatic Nonlinear Memory Power Modelling [p. 808]
Schoukens, J.
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
Sciuto, D.
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors [p. 252]
Sciuto, D.
Functional Test Generation for Behaviorally Sequential Models [p. 403]
Sechen, C.
Automatic Datapath Tile Placement and Routing [p. 552]
Serdar, T.
Automatic Datapath Tile Placement and Routing [p. 552]
Shah, R.
Design Methodology for PicoRadio Networks [p. 314]
Shamberger, J.
Design Methodology for PicoRadio Networks [p. 314]
Sheets, M.
Design Methodology for PicoRadio Networks [p. 314]
Sheng, S.
Efficient Spectral Techniques for Sequential ATPG [p. 204]
Shin, D.
An Operation Rearrangement Technique for Power Optimization in VLIW Instruction Fetch [p. 809]
Siegmund, R.
SystemCSV -- An Extension of SystemC for Mixed Multi-Level Communication Modeling and Interface-Based System Design [p. 26]
Silvano, C.
Exploiting Data Forwarding to Reduce the Power Budget of VLIW Embedded Processors [p. 252]
Sonza Reorda, M.
On the Test of Microprocessor IP Cores [p. 209]
Sonza Reorda, M.
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
Squillero, S.
On the Test of Microprocessor IP Cores [p. 209]
Stuikys, V.
Two Approaches for Developing Generic Components in VHDL [p. 800]
Suzuoki, M.
CPU for PlayStation®2 [p. 696]
Svarstad, K.
A Model for Describing Communication between Aggregate Objects in the Specification and Design of Embedded Systems [p. 77]

T

Tago, H.
CPU for PlayStation®2 [p. 696]
Takahashi, A.
Clustering Based Fast Clock Scheduling for Light Clock-Tree [p. 240]
Tamesada, T.
CMOS Open Defect Detection by Supply Current Test [p. 509]
Teica, E.
On the Verification of Synthesized Designs Using Automatically Generated Transformational Witnesses [p. 798]
Teich, J.
Optimal FPGA Module Placement with Temporal Precedence Constraints [p. 658]
Terechko, A.
PRMDL: A Machine Description Language for Clustered VLIW Architectures [p. 821]
Theeuwen, F.
Automatic Nonlinear Memory Power Modelling [p. 808]
Thornton, M.
Spectral Decision Diagrams Using Graph Transformations [p. 713]
Thurner, T.
Vehicle Electric/Electronic Architecture -- One of the Most Important Challenges for OEM's [p. 112]
Tuan, T.
Design Methodology for PicoRadio Networks [p. 314]

U

Ubar, R.
Timing Simulation of Digital Circuits with Binary Decision Diagrams [p. 460]

V

Valencia, M.
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation Delay Model [p. 467]
van de Goor, A.
Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs [p. 496]
van der Werf, A.
Power-Efficient Layered Turbo Decoder Processor [p. 246]
van der Werf, A.
Functional Units with Conditional Input/Output Behavior in VLIW Processors [p. 822]
van Eijk, K.
Constraint Satisfaction for Storage Files with Fifos or Stacks during Scheduling [p. 824]
van Eijndhoven, J.
PRMDL: A Machine Description Language for Clustered VLIW Architectures [p. 821]
van Heijningen, M.
High-Level Simulation of Substrate Noise Generation from Large Digital Circuits with Multiple Supplies [p. 326]
van Meerbergen, J.
Power-Efficient Layered Turbo Decoder Processor [p. 246]
van Staveren, A.
Order Determination for Frequency Compensation of Negative-Feedback Systems [p. 815]
van Staveren, A.
Minimizing the Number of Floating Bias Voltage Sources with Integer Linear Programming [p. 816]
Vanassche, P.
Efficient Time -Domain Simulation of Telecom Frontends Using a Complex Damped Exponential Signal Model [p. 169]
Vandersteen, G.
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
Vandersteen, G.
CAD for RF Circuits [p. 520]
Varea, M.
Dual Transitions Petri Net Based Modelling Technique for Embedded Systems Specification [p. 566]
Vazquez, P.
HALOTIS: High Accuracy LOgic TIming Simulator with Inertial and Degradation Delay Model [p. 467]
Velazco, R.
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
Vemuri, R.
Hierarchical Memory Mapping during Synthesis in FPGA -Based Reconfigurable Computers [p. 650]
Vemuri, R.
On the Verification of Synthesized Designs Using Automatically Generated Transformational Witnesses [p. 798]
Vemuri, R.
A Regularity-Based Hierarchical Symbolic Analysis Method for Large-Scale Analog Networks [p. 806]
Verhoeven, C.
Order Determination for Frequency Compensation of Negative-Feedback Systems [p. 815]
Verhoeven, C.
Minimizing the Number of Floating Bias Voltage Sources with Integer Linear Programming [p. 816]
Verkest, D.
Task Concurrency Management Methodology Summary [p. 813]
Vierhaus, H.
A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in Embedded Processors [p. 811]
Violante, M.
On the Test of Microprocessor IP Cores [p. 209]
Violante, M.
System Safety through Automatic High-Level Code Transformations: An Experimental Evaluation [p. 297]
Vital, J.
A SkillTM-Based Library for Retargetable Embedded Analog Cores [p. 768]
Vranken, H.
Circuit Partitioning for Efficient Logic BIST Synthesis [p. 86]

W

Wahl, M.
From DFT to Systems Test -- A Model Based Cost Optimization Tool [p. 302]
Wakabayashi, K.
Property-Specific Witness Graph Generation for Guided Simulation [p. 799]
Wambacq, P.
Efficient Bit-Error-Rate Estimation of Multicarrier Transceivers [p. 164]
Wambacq, P.
CAD for RF Circuits [p. 520]
Wang, K.
Binary Decision Diagram with Minimum Expected Path Length [p. 708]
Watanabe, Y.
Generation of Minimal Size Code for Schedule Graphs [p. 668]
Wehn, N.
Design of Low-Power High-Speed Maximum a Priori Decoder Architectures [p. 258]
Werner, C.
Crosstalk Noise in Future Digital CMOS Circuits [p. 331]
Wilson, R.
Managing the SoC Design Challenge with "Soft" Hardware [p. 610]
Wolf, W.
Allocation and Scheduling of Conditional Task Graph in Hardware/Software Co-Synthesis [p. 620]
Wong, C.
Task Concurrency Management Methodology Summary [p. 813]
Wong, D.
Slicing Tree is a Complete Floorplan Representation [p. 228]
Wong, D.
A Graph Based Algorithm for Optimal Buffer Insertion under Accurate Delay Models [p. 535]
Worm, A.
Design of Low-Power High-Speed Maximum a Priori Decoder Architectures [p. 258]
Wörner, A.
Crosstalk Noise in Future Digital CMOS Circuits [p. 331]
Wright, P.
Design Methodology for PicoRadio Networks [p. 314]
Wu, Y.
Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques [p. 233]
Wunderlich, H.
Circuit Partitioning for Efficient Logic BIST Synthesis [p. 86]
Wunderlich, H.
On Applying the Set Covering Model to Reseeding [p. 156]
Wunderlich, H.
Using Mission Logic for Embedded Testing [p. 805]

X

Xie, Y.
Allocation and Scheduling of Conditional Task Graph in Hardware/Software Co-Synthesis [p. 620]
Xu, Q.
Efficient and Passive Modeling of Transmission Lines by Using Differential Quadrature Method [p. 437]

Y

Yamamoto, Y.
CPU for PlayStation®2 [p. 696]
Yang, B.
CAD for RF Circuits [p. 520]
Yang, P.
Task Concurrency Management Methodology Summary [p. 813]
Yildiz, E.
Minimizing the Number of Floating Bias Voltage Sources with Integer Linear Programming [p. 816]
Yoo, S.